Semiconductor devices, such as microprocessors, optoelectronic devices, microelectromechanical devices, memory devices, such as Flash memory, DRAM chips or NROM chips, include arrays of structures as, e.g., memory cells that are arranged in rows and columns. In the exemplary case of memory cells, these devices include gate electrodes for the memory cell transistors, whereby the gate electrodes are connected by word lines, by which the memory cells are addressed.
The word lines are often formed by patterning a conductive layer stack so as to form single word lines that are arranged in parallel. The word lines are electrically insulated from one another laterally by a dielectric material. The lateral distance between two word lines and the width of a word line sum to the pitch of the array of word lines. The pitch is the dimension of the periodicity of a periodic pattern arrangement.
The word lines often form a strictly periodic pattern, in order to reduce the necessary device area as much as possible.
Likewise, bit lines for the memory cells are formed by patterning a conductive layer so as to form the single bit lines which are electrically insulated from one another by a dielectric material.
To use the potential of the existing illumination sources (e.g., lithography with wavelengths of 193 nm or 248 nm), the manufacturing of fine sublithographic structures, especially fine regular line structures, using spacer techniques, has been described, e.g., in the DE 42 35 702 A1 and DE 42 36 609 A1. In DE 42 36 609 A1 a line-by-spacer method is described to produce sublithographic spacers. In US 2006/0024621 A1 and DE 10 2004 034 572 A1 a line-by-spacer-fill and a line-by-liner-fill method are described. Line shrink methods are described in the article in Microelectronic Engineering 83, pages 730 to 733.